1. Field of the Invention
The present invention relates to the design of memory units used for storing data bits, and more specifically to a dual port memory unit implemented using a single port memory core.
2. Related Art
A memory subsystem generally contains multiple cells, with each cell storing a data bit (typically of binary value). Memory subsystems are implemented using technologies such as SRAMs (static random access memories) and DRAM (dynamic RAMs), as is well known in the relevant arts.
Access ports are often provided (in memory subsystems) to facilitate storing or retrieving the data bits in the cells. Access ports generally contains number of leads which can be connected to external devices accessing the memory subsystem. The leads in turn are typically connected to carry control signals, address information and data to perform memory related operations such as read, write, etc.
There are several prior memory subsystems, which are designed with only a single access port. In such an approach, all external systems accessing a memory subsystem share the same single access port for accessing the data in the cells contained in the memory subsystem. One problem with such single port memory subsystems is that only one access operation can be issued to the memory subsystem in a given memory clock cycle, and accordingly a sequential order is imposed on access operations when multiple devices need to access the data in such a memory subsystem.
At least to provide simultaneous access to multiple devices (in a given memory cycle), dual port or multi port subsystems are often used. In general, an access operation can be issued at each of the such multi-ports independently. Thus, each external device may issue a corresponding access operation independently (to a corresponding port) without regard to some other device issuing access operations to some other port. The effective aggregate access rate of the memory subsystem (and thus the throughput performance of a system employing the memory subsystem) may be enhanced as a result.
In one prior approach, dual port memories are implemented by employing dual-port bit cells, with each cell supporting parallel access operations corresponding to the two ports. Thus, even if the two read accesses (from two different ports) are directed to the same cell, the cell is designed to provide the stored bit value on paths corresponding to the two ports in parallel.
One problem with such an approach based on dual-port bit cells is that each dual-port cell may require more transistors than a bit-cell (“single port bit cell”) supporting only single access at any given time. For example, accordingly to one approach, a dual port cell and a single port cell respectively require 8 and 6 transistors. The enhanced number of transistors generally leads to higher area requirements, more power consumption, and additional complexity to overall implementation. Further, in one known embodiment, the dual port cell cannot support write operations (as well as combination of one write and one read) from both ports in the same memory cycle.
Accordingly, what is needed is a dual-port memory subsystem which overcomes at least some of such disadvantages.